Bit density of semiconductor memories increases four times per three years and operation speeds thereof also increase. Such development in semiconductor memories enables 1 GHz (giga hertz) operation speed for a 1 Gb (giga bit) DRAM (dynamic random access memory) device.
In DRAM devices, an 8F.sup.2 memory cell size adopted in a 64K DRAM density era has been employed up to now. The 8F.sup.2 memory cell is called as a folded bit line cell architecture in view of bit line arrangement with respect to a sense amplifier. The 8F.sup.2 is the smallest theoretical cell size of the folded bit line cell architecture. Herein, the F depicts a minimum feature size and is normally determined by a minimum design rule which can be patterned. The F may also mean half(1/2) of parallel bit line pitch comprising a memory cell array. For example, a smallest cell size of a 0.6 .mu.m pitch becomes 8.times.0.3.times.0.3=0.72 .mu.m.sup.2.
FIG. 1A shows a layout of a memory cell having an 8F.sup.2 folded bit line cell architecture of a COB (capacitor over bit line) that is mainly used in the present high-density DRAM. FIG. 1B is a cross-sectional view taken along a line 1A-1A' of FIG. 1A.
Referring to FIG. 1A and FIG. 1B, a transistor 6 having a gate electrode (word line (WL)) and source and drain regions (not shown) is formed on a semiconductor substrate 1 where a device isolation layer 2 is formed. Contact pads are formed to be electrically connected to an active region 3 between the word lines. The contact pads include a storage electrode contact pad 8a and a bit line contact pad 8b. A storage electrode 16 and a bit line 11 are formed to be respectively connected with the storage electrode contact pad 8a and the bit line contact pad 8b through selected interlayer insulating films 10, 12. Herein, the bit line 11 is formed under the storage electrode 16, i.e., the bit line 11 is formed before the formation of the storage electrode 16.
In foregoing COB memory cell architectures, since a memory cell capacitor is formed after formation of the word line (WL) and bit line 11, a memory cell contact hole 14 has an inevitably high aspect ratio. In other words, the interlayer insulating film 12 is thick and it is difficult to open a contact hole therein. To solve the problem of etching the high aspect ratio contact hole 14, a process of forming a landing pad, so called cell pad, is generally used.
It is impossible, however, to form a silicide layer simultaneously on a top surface of a gate and a source/drain in the landing pad application. As a result, it becomes complex and difficult to implement a high performance logic device and DRAM device together. In addition, the misalignment of word line or bit line may cause shorts between a memory cell and a word line, or between a memory cell and a bit line, during the step of forming memory cell contact. These inherent problems stand in the way of reduction of DRAM cell density and implementation of a large capacity and high performance DRAM cell.
Once the minimum feature size (F) is decided, a minimum cell size is decided and an area occupied by an array according to DRAM density is calculated. The area occupied by array is given as `Nbit.times.cell size`. In case of a 1 Gb DRAM, for example, the Nbit corresponds to 2.sup.30 (=1,073,741,824). The ratio of the array area with respect to a total chip size is called as `array efficiency`. The array efficiency, in case of high-density DRAM devices, such as a 64 Mb DRAM and more, is about 65%. Accordingly, the chip size is expressed by a following equation as a function of minimum feature size (F). EQU S.sub.C =.alpha..sup.-1.times.N.sub.bit.times.8F.sup.2
Herein, S.sub.C denotes a chip size and .alpha. denotes an array efficiency. The calculation of a DRAM chip size according to a minimum feature size or density in accordance with foregoing equation is shown in FIG. 2. Herein, the chip size is calculated in accordance with an 8F.sup.2 folded bit line cell architecture and array efficiency of 65% in every memory device density era.
In FIG. 2, it is expected that a 1 Gb chip size will be about 425 mm.sup.2, 4 Gb about 960 mm.sup.2, and 16 Gb about 2000 mm.sup.2. It is expected to be very difficult to obtain a good chip yield from such a large chip size and it is well known that the yield is in inverse proportion to a chip size. For a cost-effective high-density DRAM, therefore, it is a necessary that a memory cell size be made from the same minimum feature size. It is well known in the art that the minimum cell size of an open line cell architecture is 6F.sup.2 (remember that 8F.sup.2 is the minimum cell size of the folded bit line cell structure). The open bit line cell architecture is disadvantageous, however, because of its inferior noise immunity and because of difficulty in the sense amplifier layout.
A combined approach of open bit line layout and folded bit line sensing has also been recently reported. This approach is also disadvantageous, however, as it requires an additional mask.